A packet switch typically includes a crossbar switch for routing packets. In this type of packet switch, packets are received at ingress ports and stored in respective ingress buffers. An arbiter then selects packets stored in the ingress buffers, and the crossbar switch simultaneously routes the selected packets to egress ports of the packet switch. In turn, the egress ports store the selected packets in respective egress buffers and then output the selected packets from the packet switch.
One metric for measuring performance of a packet switch is throughput. Throughput is typically defined as the number of packets routed through a packet switch in a given time period. Moreover, throughput of a packet switch may be adversely affected if the storage capacity of an ingress buffer in the packet switch is insufficient for a particular application of the packet switch. For this reason, storage capacities of ingress buffers are often important criteria in designing a packet switch. Because the throughput of a packet switch depends upon the storage capacities of the ingress buffers in the packet switch as well as the particular application of the packet switch, selection of the storage capacities often results in less than optimum throughput for different applications of the packet switch.
In some types of packet switches, an ingress port includes multiple ingress buffers, each of which is dedicated to a particular packet type. For example, an ingress port of a packet switch compliant with the peripheral component interconnect express (PCIe) 2.0 standard typically includes an ingress buffer for posted packets, another ingress buffer for non-posted packets, and still another ingress buffer for completion packets. In these types of packet switches, throughput may be adversely affected if the storage capacity of any of the ingress buffers of an ingress port is insufficient for a particular application of the packet switch.
In light of the above, a need exists for increasing throughput of a packet switch. A further need exists for increasing throughput of a packet switch compliant with the PCIe 2.0 standard.